1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device having a gate electrode provided with a depletion layer.
2. Description of the Background Art
A semiconductor device having a gate electrode provided with a depletion layer is known in general. The conventional semiconductor device is constituted of a source region, a drain region, a gate insulating film formed on a channel region located between the source region and the drain region and a gate electrode formed on the gate insulating film. In this semiconductor device, the gate electrode has a low impurity concentration on an end thereof and a high impurity concentration at the center thereof. Thus, a depletion layer can be formed on an end of the gate electrode. Consequently, the distance between the gate electrode and the drain region is increased due to the depletion layer provided on the end of the gate electrode and located between the gate electrode and the drain region, whereby an electric field between the gate electrode and the drain region is reduced. Thus, the withstand voltage of a transistor can be improved, and a gate insulating film can be prevented from electric field concentration.
In the aforementioned semiconductor device, however, the depletion layer is formed only on the end of the gate electrode, and the most part of the gate electrode functions as the electrode. When the semiconductor device is applied to a double-diffused transistor offsetting a drain with a gate electrode, therefore, a gate field is insufficiently suppressed in a drift layer region, and the parasitic capacitance between the gate electrode and a substrate is disadvantageously increased.